1. Field of the Invention
The present invention relates to a semiconductor memory device having a planar cell structure.
2. Description of the Related Art
In general, a MOS type semiconductor integrated circuit device is formed in such a way that a field oxide film is used for device isolation and that a source region and a drain region are formed by diffusing impurities in a substrate by a self-alignment method with the use of a gate electrode as a mask. One or two contacts are required for connecting the source region and the drain region per one transistor. It is therefore necessary for the margin to take a space for the contacts and wirings, which impedes the realization of high integration of a device.
In order to improve this point, a semiconductor integrated circuit device having a planar cell structure has been proposed in Japanese Patent Application Laying Open (KOKAI) Nos. 61-288464 and 63-96953. In the planar cell structure, the first continuous diffusion region for a plurality of MOS transistor source regions and the second continuous diffusion region for a plurality of MOS transistor drain regions are formed in parallel to each other on a substrate. A word line is formed crossing over the both diffusion regions on the substrate through an electrically insulating film.
In the planar cell structure, it becomes unnecessary to form a field oxide film for device isolation. The source region and the drain region are formed to be used in common to a plurality of MOS transistors. It is therefore sufficient to provide one contact in proportion to several or several tens of transistors, which makes it possible to realize a compact IC device of high density.
An embodiment of a conventional planar cell structure is shown in FIGS. 1a and 1b. FIG. 1a shows a memory part and FIG. 1b is a cross-sectional view showing a little simplified memory part, together with one portion of a peripheral transistor part.
A channel stopper layer 54 and a field oxide film 58 are formed in order to isolate the peripheral transistor part from the memory part and also isolate the peripheral transistors from each other.
In the memory part, continuous N-type diffusion layers 42s, 42d for constituting a plurality of memory transistors are formed in strips in parallel to each other. Word lines 48 constituted by a polycrystalline silicon layer and functioning also as a gate electrode is formed on a substrate 40 through a gate oxide film 44 as well as on the diffusion layers 42s, 42d through a silicon oxide film 46 thicker than the gate oxide film 44. Each of the word lines 48 extends in a direction crossing perpendicularly over a longitudinal direction of the diffusion layers 42s, 42d.
In the peripheral transistor part, reference numeral 50s denotes a source, 50d denotes a drain. A gate electrode 52 constituted by a polycrystalline silicon layer is formed through a gate oxide film 44 on the substrate 40.
In the memory part, the rectangular area 54 defined by a dash-dot line (FIG. 1a) represents one memory transistor. In each memory transistor, a threshold value thereof is adjusted and set by controlling an ion implantation in order to determine a ROM code thereof. For example, the threshold value is raised by implanting boron into a channel region of each memory transistor, or the threshold value is kept low by not implanting impurities into the channel region. When the word line 48 of the memory transistor 54 is selected and a voltage is applied thereto, if the threshold value of the memory transistor 54 is low, current flows from a bit line (drain) 42d to the source 42s. On the other hand, if the threshold value is high, a current does not flow so that the data stored in ROM can be read by a sensing circuit connected to the bit line 42d.
In the planar cell structure, when a more minute device is intended to be produced, a miniaturization of the device is impeded due to a short channel effect caused by the diffusion layers 42s, 42d. In an ordinal MOS transistor such as the peripheral transistor, the problem of the short channel effect can be avoided by employing Lightly Doped Drain (LDD) structure for the diffusion layers, while it is structurally difficult to employ the LDD structure for the planar cell structure.
Since the bit line 42d and the source 42s are constituted by the diffusion layers formed on the substrate 40, a resistance value is high. Also, junctions are formed on bases and side walls of the drain 42d and the source 42s thereby to produce parasitic capacity. Therefore, it can be considered that a functional speed of the device is delayed by these high resistance and parasitic capacity.